Practical, fast Monte Carlo statistical static timing analysis: why and how
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Two fast methods for estimating the minimum standby supply voltage for large SRAMs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As VLSI technology moves to the nanometer scale for transistor feature sizes, the impact of manufacturing imperfections result in large variations in the circuit performance. Traditional CAD tools are not well-equipped to handle this scenario, since they do not model this statistical nature of the circuit parameters and performances, or if they do, the existing techniques tend to be over-simplified or intractably slow. We draw upon ideas for attacking parallel problems in other technical fields, such as computational finance, machine learning and hydrology, and synthesize them with innovative attacks for our problem domain of integrated circuits, to develop novel solutions to problems of efficient statistical analysis of circuits in the nanometer regime. In particular, this thesis makes three contributions: (1) SiLVR, a nonlinear response surface modeling (RSM) and performance-driven dimensionality reduction strategy, that uses the concepts of projection pursuit and latent variable regression to obtain an absolute improvement in modeling error of up to 34%, over the best quadratic RSM method. SiLVR also captures the designer's insight into the circuit behavior, by automatically extracting quantitative measures of relative global sensitivities and nonlinear correlation. (2) Fast Monte Carlo simulation of circuits using quasi-Monte Carlo, showing speedups of 2× to 50× over standard Monte Carlo. (3) Statistical blockade, an efficient method for sampling rare events and estimating their probability distribution using limit results from extreme value theory, applied to high replication circuits like SRAM cells.