Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Algorithm 823: Implementing scrambled digital sequences
ACM Transactions on Mathematical Software (TOMS)
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Proceedings of the 42nd annual Design Automation Conference
Statistical delay computation considering spatial correlations
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Projection-based performance modeling for inter/intra-die variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 43rd annual Design Automation Conference
A framework for statistical timing analysis using non-linear delay and slew models
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
An accurate sparse matrix based framework for statistical static timing analysis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Low discrepancy sequences in high dimensions: How well are their projections distributed?
Journal of Computational and Applied Mathematics
Novel algorithms for fast statistical analysis of scaled circuits
Novel algorithms for fast statistical analysis of scaled circuits
Proceedings of the conference on Design, automation and test in Europe
Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust Extraction of Spatial Correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variational capacitance extraction of on-chip interconnects based on continuous surface model
Proceedings of the 46th Annual Design Automation Conference
Proceedings of the 47th Design Automation Conference
Practical Monte-Carlo based timing yield estimation of digital circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Statistical static timing analysis using Markov chain Monte Carlo
Proceedings of the Conference on Design, Automation and Test in Europe
Advanced variance reduction and sampling techniques for efficient statistical timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Residue arithmetic for variation-tolerant design of multiply-add units
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Exponent monte carlo for quick statistical circuit simulation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Accelerated statistical simulation via on-demand Hermite spline interpolations
Proceedings of the International Conference on Computer-Aided Design
The effect of random dopant fluctuations on logic timing at low voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast analog circuit yield estimation method for medium and high dimensional problems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Statistical static timing analysis (SSTA) has emerged as an essential tool for nanoscale designs. Monte Carlo methods are universally employed to validate the accuracy of the approximations made in all SSTA tools, but Monte Carlo itself is never employed as a strategy for practical SSTA. It is widely believed to be "too slow" -- despite an uncomfortable lack of rigorous studies to support this belief. We offer the first large-scale study to refute this belief. We synthesize recent results from fast quasi-Monte Carlo (QMC) deterministic sampling and efficient Karhunen-Loéve expansion (KLE) models of spatial correlation to show that Monte Carlo SSTA need not be slow. Indeed, we show for the ISCAS89 circuits, a few hundred, well-chosen sample points can achieve errors within 5%, with no assumptions on gate models, wire models, or the core STA engine, with runtimes less than 90 s.