Practical Monte-Carlo based timing yield estimation of digital circuits

  • Authors:
  • Javid Jaffari;Mohab Anis

  • Affiliations:
  • University of Waterloo, Waterloo, ON, Canada;University of Waterloo, Waterloo, ON, Canada

  • Venue:
  • Proceedings of the Conference on Design, Automation and Test in Europe
  • Year:
  • 2010

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Abstract

The advanced sampling and variance reduction techniques as efficient alternatives to the slow crude-MC method have recently been adopted for the analysis of timing yield in digital circuits. However, these techniques, the Quasi-MC method and the order-statistics base estimator, are prone to bias or negligible improvement upon the crude-MC method when an early-stage timing analysis with few (10s) simulation iterations can be afforded. In this paper, these issues are studied and a control variate-base technique is developed to accurately estimate the moments of circuits' critical delays with very few timing simulation iterations. A skew-normal distribution is then used to form a closed-form cumulative distribution function of timing yield. Analysis of the benchmark circuits shows 3--10X reduction of the confidence interval ranges of the estimated yield compared to the crude-MC translating to 9--100X reduction in the number of samples for the same analysis accuracy.