Timing yield estimation of digital circuits using a control variate technique

Authors:
Javid Jaffari;Mohab Anis
Affiliations:
ECE Department, University of Waterloo, ON, Canada N2L 3G1;ECE Department, University of Waterloo, ON, Canada N2L 3G1
Venue:
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Year:
2009

Citing 0
Cited 2

Practical Monte-Carlo based timing yield estimation of digital circuits

Proceedings of the Conference on Design, Automation and Test in Europe
A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials

ACM Transactions on Design Automation of Electronic Systems (TODAES)

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Abstract

The Monte-Carlo (MC) technique is a traditional solution for reliable yield analysis, and in contrast to probabilistic methods it can account for any complicated timing and process variation models. However, a precise analysis that involves a traditional MC-based technique requires many simulation iterations, especially for the extreme quantile values. In this paper, a new yield estimator is developed for the timing yield of digital circuits based on an auxiliary (control) variable which is formed by extracting the delay equation of the nominally critical path. The superiority of the proposed technique is studied and verified against the crude-MC and the advanced sampling techniques, Latin Hypercube Sampling and Quasi-MC. The technique shows significant (2X to 30X) runtime improvement over the crude-MC by reducing the required number of iterations to achieve a maximum confidence interval.