Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 42nd annual Design Automation Conference
Correlation-aware statistical timing analysis with non-gaussian delay distributions
Proceedings of the 42nd annual Design Automation Conference
A general framework for accurate statistical timing analysis considering correlations
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Efficient Monte Carlo based incremental statistical timing analysis
Proceedings of the 45th annual Design Automation Conference
Characterization of Standard Cells for Intra-Cell Mismatch Variations
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Practical, fast Monte Carlo statistical static timing analysis: why and how
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 46th Annual Design Automation Conference
Statistical-Variability Compact-Modeling Strategies for BSIM4 and PSP
IEEE Design & Test
Non-linear operating point statistical analysis for local variations in logic timing at low voltage
Proceedings of the Conference on Design, Automation and Test in Europe
VLSID '11 Proceedings of the 2011 24th International Conference on VLSI Design
Statistical timing analysis of combinational logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical Timing Analysis: From Basic Principles to State of the Art
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In order to achieve ultra-low power (ULP), ICs are being designed for VDD ≤ 0.5 V. At these low voltages, random dopant fluctuations (RDFs) result in a stochastic component of logic delay that can be comparable to the global corner delay. Moreover, the probability density function (PDF) of this stochastic delay can be highly non-Gaussian. In order to predict the statistical impact of RDF-induced local variations on logic timing, it is necessary to incorporate these effects into a timing closure methodology. This paper presents a computationally efficient methodology for stochastic characterization of standard cell libraries at low voltage, where the cell delay is a nonlinear function of the transistor random variables (RVs), and the resulting cell delay has a non-Gaussian PDF. It also presents a computationally efficient methodology for computing any point on the PDF of a timing path (TP) delay, in the case where cell delays are non-Gaussian. The method is called nonlinear operating point analysis of local variation (NLOPALV). The general NLOPALV theory is developed. It is applied to cell library characterization, and the accuracy of the NLOPALV approach is validated by comparison to Monte Carlo simulation. NLOPALV is also applied to timing path analysis on a 28 nm DSP IC. The approach has been implemented using commercial CAD tools, and integrated into a commercial IC design flow. The NLOPALV approach gives timing results that are within 5% accuracy compared to Monte Carlo analysis at VDD = 0.5 V. This compares to errors on the order of 50% when the Gaussian approximation is used.