Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On Statistical Timing Analysis with Inter- and Intra-Die Variations
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design for Manufacturability and Statistical Design: A Comprehensive Approach
Design for Manufacturability and Statistical Design: A Comprehensive Approach
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Characterization of Standard Cells for Intra-Cell Mismatch Variations
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
The effect of random dopant fluctuations on logic timing at low voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ≤ 0.5V), the standard deviation of gate delay becomes comparable to nominal delay, and the Probability Density Function (PDF) of the gate delay is highly non-Gaussian. This paper presents a computationally efficient algorithm for computing the PDF of logic Timing Path (TP) delay, which results from local variations. This approach is called Non-linear Operating Point Analysis for Local Variations (NLOPALV). The approach is implemented using commercial STA tools and integrated into the standard CAD flow using custom scripts. Timing paths from a 28nm commercial DSP are analyzed using the proposed technique and the performance is observed to be within 5% accuracy compared to SPICE based Monte-Carlo analysis.