Timing analysis with compact variation-aware standard cell models
Integration, the VLSI Journal
Non-linear operating point statistical analysis for local variations in logic timing at low voltage
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 48th Design Automation Conference
The effect of random dopant fluctuations on logic timing at low voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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With the adoption of statistical timing across industry, there is a need to characterize all gates/cells in a digital library for delay variations (referred to as, statistical characterization). Statistical characterization need to be performed efficiently with acceptable accuracy as a function of several process and environment parameter variations. In this paper, we propose an approach to consider intra-cell process mismatch variations to characterize a cell's delay and output transition time (output slew) variations. A straightforward approach to address this problem is to model these mismatch variations by characterizing for each device fluctuation separately. However, the runtime complexity for such characterization becomes of the order of number of devices in the cell and the number of simulations required can easily become infeasible. We analyze the fluctuations in switching and non-switching devices and their impact on delay variations. Using these properties of the devices, we propose a clustering approach to characterize for cell's delay variations due to intra-cell mismatch variations. The proposed approach results in as much as 12X runtime improvements with acceptable accuracy, compared with Monte Carlo simulations. We show that this approach ensures an upper-bound on the results while keeping the number of simulations for each cell independent of the number of devices.