First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Fast, non-Monte-Carlo estimation of transient performance variation due to device mismatch
Proceedings of the 44th annual Design Automation Conference
Challenges in gate level modeling for delay and SI at 65nm and below
Proceedings of the 45th annual Design Automation Conference
Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution
Proceedings of the 45th annual Design Automation Conference
Characterization of Standard Cells for Intra-Cell Mismatch Variations
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Proceedings of the 46th Annual Design Automation Conference
Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexity
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents an approach for statistical characterization of standard cells based on a combination of Statistical Design of Experiments (S-DoE) and Response Surface Modeling. Unlike both, most of the State-of-the-Art and Sensitivity Analysis (SA) techniques currently offered by EDA vendors, S-DoE preserves the underlying correlation among process variation parameters. This results in about two orders of magnitude of statistical accuracy improvement, yet it features an electrical simulation effort linear to the cell complexity. The technique is validated using a representative subset of standard cells using a 32nm statistical Physical Design Kit.