Challenges in gate level modeling for delay and SI at 65nm and below

Authors:
Igor Keller;King Ho Tam;Vinod Kariat
Affiliations:
Cadence Design Systems, Inc., San Jose, CA;Cadence Design Systems, Inc., San Jose, CA;Cadence Design Systems, Inc., San Jose, CA
Venue:
Proceedings of the 45th annual Design Automation Conference
Year:
2008

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Abstract

In this paper we review the prior art and recent advances in the area of standard cell modeling for delay and noise analyses, suggest a taxonomy of different cell models, and discuss their strengths and weaknesses. We also discuss challenges in cell modeling for delay and noise analyses arising in new submicron process nodes.