Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning
Proceedings of the 2009 International Conference on Computer-Aided Design
SPIRE: a retiming-based physical-synthesis transformation system
Proceedings of the International Conference on Computer-Aided Design
A statistical model of logic gates for Monte Carlo simulation including on-chip variations
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
The effect of random dopant fluctuations on logic timing at low voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel path-based algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have been implemented in the context of the EinsTimer static timing analyzer. The three methods are complementary in that they are designed to target different process variation conditions that occur in practice. Numerical results are presented to study the strengths and weaknesses of these complementary approaches. Timing analysis results in the face of statistical temperature and Vdd variations are presented on an industrial ASIC part on which a bounded timing methodology leads to surprisingly wrong results