Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
The System Designer's Guide to VHDL-AMS
The System Designer's Guide to VHDL-AMS
Design for Variability in DSM Technologies
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Statistical estimation of leakage current considering inter- and intra-die process variation
Proceedings of the 2003 international symposium on Low power electronics and design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Parametric yield estimation considering leakage variability
Proceedings of the 41st annual Design Automation Conference
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Statistical timing analysis of combinational logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exponent monte carlo for quick statistical circuit simulation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Process variations are becoming a paramount design problem in nano-scale VLSI. We present a framework for the statistical model of logic gates that describes both inter-die and intra-die variations of performance parameters such as propagation delay and leakage currents. This allows fast but accurate behavioral-level Monte-Carlo simulations, that could be useful for full-custom digital design optimization and yield prediction, and enables the development of a yield-aware digital design flow. The model can incorporate correlation between mismatch parameters and dependence on distance and position, and can be extracted by fitting of Monte-Carlo transistor level simulations. An example implementation using Verilog-A hardware description language in Cadence environment is presented.