A fast analog circuit yield estimation method for medium and high dimensional problems

Authors:
Bo Liu;Jarir Messaoudi;Georges Gielen
Affiliations:
ESAT-MICAS, Katholieke Universiteit Leuven, Leuven, Belgium;ESAT-MICAS, Katholieke Universiteit Leuven, Leuven, Belgium;ESAT-MICAS, Katholieke Universiteit Leuven, Leuven, Belgium
Venue:
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2012

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Abstract

Yield estimation for analog integrated circuits remains a time-consuming operation in variation-aware sizing. State-of-the-art statistical methods such as ranking-integrated Quasi-Monte-Carlo (QMC), suffer from performance degradation if the number of effective variables is large (as typically is the case for realistic analog circuits). To address this problem, a new method, called AYLeSS, is proposed to estimate the yield of analog circuits by introducing Latin Supercube Sampling (LSS) technique from the computational statistics field. Firstly, a partitioning method is proposed for analog circuits, whose purpose is to appropriately partition the process variation variables into low-dimensional sub-groups fitting for LSS sampling. Then, randomized QMC is used in each sub-group. In addition, the way to randomize the run order of samples in Latin Hypercube Sampling (LHS) is used for the QMC sub-groups. AYLeSS is tested on 4 designs of 2 example circuits in 0.35 μm and 90nm technologies with yield from about 50% to 90%. Experimental results show that AYLeSS has approximately a 2 times speed enhancement compared with the best state-of-the-art method.