Breaking the simulation barrier: SRAM evaluation through norm minimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Statistical static timing analysis using Markov chain Monte Carlo
Proceedings of the Conference on Design, Automation and Test in Europe
Enrichment of limited training sets in machine-learning-based analog/RF test
Proceedings of the Conference on Design, Automation and Test in Europe
Two fast methods for estimating the minimum standby supply voltage for large SRAMs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN
Proceedings of the Conference on Design, Automation and Test in Europe
Multidimensional analog test metrics estimation using extreme value theory and statistical blockade
Proceedings of the 50th Annual Design Automation Conference
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Circuit reliability under statistical process variation is an area of growing concern. For highly replicated circuits such as SRAMs and flip flops, a rare statistical event for one circuit may induce a not-so-rare system failure. The authors of [1] proposed Statistical Blockade as a Monte Carlo technique that allows us to efficiently filter--to block--unwanted samples insufficiently rare in the tail distributions we seek. However, there are significant practical problems with the technique. In this work, we show common scenarios in SRAM design where these problems render Statistical Blockade ineffective. We then propose significant extensions to make Statistical Blockade practically usable in these common scenarios. We show speedups of 102+ over standard Statistical Blockade and 104+ over standard Monte Carlo, for an SRAM cell in an in- dustrial 90nm technology.