ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 43rd annual Design Automation Conference
Analytical modeling of SRAM dynamic stability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Analyzing static and dynamic write margin for nanometer SRAMs
Proceedings of the 13th international symposium on Low power electronics and design
SRAM dynamic stability: theory, variability and analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
On the efficacy of write-assist techniques in low voltage nanoscale SRAMs
Proceedings of the Conference on Design, Automation and Test in Europe
Accurate estimation of SRAM dynamic stability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Circuit reliability in the presence of variability is a major concern for SRAM designers. With the size of memory ever increasing, Monte Carlo simulations have become too time consuming for margining and yield evaluation. In addition, dynamic write-ability metrics have an advantage over static metrics because they take into account timing constraints. However, these metrics are much more expensive in terms of runtime. Statistical blockade is one method that reduces the number of simulations by filtering out non-tail samples, however the total number of simulations required still remains relatively large. In this paper, we present a method that uses sensitivity analysis to provide a total speedup of ~112X compared with recursive statistical blockade with only a 3% average loss in accuracy. In addition, we show how this method can be used to calculate dynamic VMIN and to evaluate several write assist methods.