Statistical analysis of SRAM cell stability
Proceedings of the 43rd annual Design Automation Conference
Analytical modeling of SRAM dynamic stability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the efficacy of write-assist techniques in low voltage nanoscale SRAMs
Proceedings of the Conference on Design, Automation and Test in Europe
A black box method for stability analysis of arbitrary SRAM cell structures
Proceedings of the Conference on Design, Automation and Test in Europe
On the impact of gate oxide degradation on SRAM dynamic and static write-ability
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Assessment of structure variation in silicon nanowire FETs and impact on SRAM
Microelectronics Journal
Minimum energy operation for clustered island-style FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Functionality and stability analysis of a 400mV quasi-static RAM (QSRAM) bitcell
Microelectronics Journal
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN
Proceedings of the Conference on Design, Automation and Test in Europe
Nonrandom device mismatch considerations in Nanoscale SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper analyzes write ability for SRAM cells in deeply scaled technologies, focusing on the relationship between static and dynamic write margin metrics. Reliability has become a major concern for SRAM designs in modern technologies. Both local mismatch and scaled VDD degrade read stability and write ability. Several static approaches, including traditional SNM, BL margin, and the N-curve method, can be used to measure static write margin. However, static approaches cannot indicate the impact of dynamic dependencies on cell stability. We propose to analyze dynamic write ability by considering the write operation as a noise event that we analyze using dynamic stability criteria. We also define dynamic write ability as the critical pulse width for a write. By using this dynamic criterion, we evaluate the existing static write margin metrics at normal and scaled supply voltages and assess their limitations. The dynamic write time metric can also be used to improve the accuracy of VCCmin estimation for active VDD scaling designs.