Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs

Authors:
Daeyeon Kim;Vikas Chandra;Robert Aitken;David Blaauw;Dennis Sylvester
Affiliations:
University of Michigan, Ann Arbor, MI, USA;ARM, Inc., San Jose, CA, USA;ARM, Inc., San Jose, CA, USA;University of Michigan, Ann Arbor, MI, USA;University of Michigan, Ann Arbor, MI, USA
Venue:
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Year:
2011

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Abstract

As process technology scales, SRAM robustness is compromised. In addition, lowering the supply voltage to reduce power consumption further reduces the read and write margins. To maintain robustness, a new bitcell topology, 8-T bitcell, has been proposed and read where write operation can be separately optimized. However, it can aggravate the half select disturb when write word-line boosting is applied or the bitcell sizing is done to enable robust writability. The half select disturb issue limits the use of a bit-interleaved array configuration required for immunity to soft errors. The opposing characteristic between write operation and half select disturb generates a new constraint which should be carefully considered for robust operation of voltage-scaled bit-interleaved 8-T SRAMs. In this paper, we propose bit-interleaved writability analysis that captures the double-sided constraints placed on the word-line pulse width and voltage level to ensure writability while avoiding half select disturb issue. Using the proposed analysis, we investigate the effectiveness of word-line boosting and device sizing optimization on improving bitcell robustness in low voltage region. With 57.7% of area overhead and 0.1V of word-line boosting, we can achieve 4.6Ã of Vth mismatch tolerance at 0.6V and it shows 41% of energy saving.