Analog Integrated Circuits and Signal Processing - Special issue: low-voltage low-power analog integrated circuits
Analytical modeling of SRAM dynamic stability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Analyzing static and dynamic write margin for nanometer SRAMs
Proceedings of the 13th international symposium on Low power electronics and design
SRAM dynamic stability: theory, variability and analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 47th Design Automation Conference
A black box method for stability analysis of arbitrary SRAM cell structures
Proceedings of the Conference on Design, Automation and Test in Europe
Challenges and Directions for Low-Voltage SRAM
IEEE Design & Test
Accurate estimation of SRAM dynamic stability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quantifying Dynamic Stability of Genetic Memory Circuits
IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB)
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The development of low-voltage SRAM bitcells with ultra-low static power consumption has become a primary focus of memory design in recent years. The analysis of these bitcells requires the evaluation of dynamic noise margin metrics in addition to the traditional static noise margins. In this paper, we extend the presentation of our recently proposed quasi-static RAM (QSRAM) cell that employs an aggressive internal feedback technique for leakage suppression. In addition to the presentation of the QSRAM circuit topology and operation, a broad stability analysis of the cell is introduced, proving the functionality and bi-stability of the bitcell. Many of the recently proposed dynamic stability metrics used in this analysis have been demonstrated on standard SRAM bitcells; however, this is one of the first times these metrics have been used to analyze the functionality of an alternative implementation. Functionality of the proposed bitcell is shown for a sub-threshold 400mV supply voltage, providing a typical leakage reduction of 21X-45X as compared to a standard two-port bitcell operating at its nominal voltage. An 8kb QSRAM array was implemented and fabricated in a commercial low-power 40nm process demonstrating full functionality and ultra-low power consumption under a sub-threshold 400mV supply.