Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Design, layout and verification of an FPGA using automated tools
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Modeling routing demand for early-stage FPGA architecture development
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Analyzing static and dynamic write margin for nanometer SRAMs
Proceedings of the 13th international symposium on Low power electronics and design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
ABC: an academic industrial-strength verification tool
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
The VTR project: architecture and CAD for FPGAs from verilog to routing
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Limit study of energy & delay benefits of component-specific routing
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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Despite the advantages offered by field-programmable gate arrays (FPGAs) for low-power systems requiring flexible computing resources, applications with the lowest power budgets still favor microprocessors and application-specific integrated circuits (ASICs). In order for such systems to exploit FPGAs, an FPGA achieving minimum energy operation is needed. Minimum energy points have been found for ASICs and microprocessors to occur at operating voltages that are typically below the transistor threshold voltage. This paper presents two clustered island-style test chips capable of operating with a single supply voltage as low as 260 mV. This supply voltage represents the lowest voltage at which an FPGA has been successfully programmed. Test chip measurements show that the minimum energy point of both circuits is at or below this minimum operating voltage. Operation at 260 mV leads to a 40X power-delay product reduction vs. 1.5V operation. The results demonstrate a clear path forward for fabricating low voltage FPGAs that are fully compatible with existing tool flows.