Field-programmable gate arrays
Field-programmable gate arrays
On routability prediction for field-programmable gate arrays
DAC '93 Proceedings of the 30th international Design Automation Conference
A fast routability-driven router for FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A coarse-grained FPGA architecture for high-performance FIR filtering
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A stochastic model for the interconnection topology of digital circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
The stratixπ routing and logic architecture
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Wiring requirement and three-dimensional integration technology for field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Technology mapping and architecture evalution for k/m-macrocell-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computers
Interconnect estimation for FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RAT: RC Amenability Test for Rapid Performance Prediction
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Wirelength modeling for homogeneous and heterogeneous FPGA architectural development
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
FPGA architecture optimisation using geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An analytical model relating FPGA architecture parameters to routability
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on CAPA'09, Special Section on WHS'09, and Special Section VCPSS' 09
Minimum energy operation for clustered island-style FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Towards development of an analytical model relating FPGA architecture parameters to routability
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An Analytical Model for Evaluating Static Power of Homogeneous FPGA Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Architecture development for FPGAs has typically been a very empirical discipline, requiring the synthesis of benchmark circuits into candidate architectures. This is difficult to do in the early stages of architecture development, however, because there is no complete architecture to synthesize circuits into. The effort required to create prototype tools for nascent architectures is far too great for every new logic block or routing architecture idea, and so it would be extremely helpful to have a simple and intuitive FPGA interconnect model to guide the architect In this paper we present such an interconnect model for island-style FPGAs, whose single output is the estimated routing demand (often referred to as W, the number of routing tracks per channel) for an FPGA as a function of several logic block, circuit and routing architecture parameters. The goal of this model is to be as simple as possible, while still accurate enough to be useful, to provide understanding and intuition on FPGA routing. Our methodology is empirical -- we propose model forms based on empirical observations, intuition and some derivation, and then fit models to experimentally generated data We show the development of the model in stages, beginning with a fully flexible FPGA, and gradually proceeding to one which includes the key parameters that control the flexibility of FPGA routing, and one key parameter describing the logic block and another relating to the typical circuit. We then show how to use these models in early-stage architecture development to provide feedback on several aspects of logic block architecture. We also show how the model can be used to explore the routing architecture space itself and to provide an overall intuition for architecture development