The memory/logic interface in FPGA's with large embedded memory arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Prediction of interconnect fan-out distribution using Rent's rule
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation
Proceedings of the 2003 international workshop on System-level interconnect prediction
Toward the accurate prediction of placement wire length distributions in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computers
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
Modeling routing demand for early-stage FPGA architecture development
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
The effect of LUT and cluster size on deep-submicron FPGA performance and density
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
A priori wirelength and interconnect estimation based on circuit characteristics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA architecture optimisation using geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An analytical model relating FPGA architecture parameters to routability
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Towards development of an analytical model relating FPGA architecture parameters to routability
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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This paper describes an analytical model that relates the architectural parameters of an FPGA to the average prerouting wirelength of an FPGA implementation. Both homogeneous and heterogeneous FPGAs are considered. For homogeneous FPGAs, the model relates the lookup-table size, the cluster size, and the number of inputs per cluster to the expected wirelength. For heterogeneous FPGAs, the number and positioning of the embedded blocks, as well as the number of pins on each embedded block is considered. Two applications of the model to FPGA architectural design are also presented.