Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Communication-oriented design space exploration for reconfigurable architectures
EURASIP Journal on Embedded Systems
Wirelength modeling for homogeneous and heterogeneous FPGA architectural development
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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As the capacities of field-programmable gate arrays (FPGAs) grow, they will be used to implement much larger circuits than ever before. These larger circuits often require significant amounts of storage. In order to address these storage requirements, FPGAs with large embedded memory arrays are now being developed by several vendors. One of the crucial components of an FPGA with on-chip memory is the routing structure between the memory arrays and logic resources. If this memory/logic interface is not flexible enough, many circuits will be unroutable, while if it is too flexible, it will be slower and consume more chip area than is necessary. In this paper, we show that an interconnect in which each memory pin can connect to between four and seven logic routing tracks is best in terms of both area and speed. We also show that by adding switches to support nets that connect multiple memory arrays, we can reduce the memory access time by up to 25% and improve the routability slightly.