RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Estimating routing congestion using probabilistic analysis
Proceedings of the 2001 international symposium on Physical design
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Interconnect resource-aware placement for hierarchical FPGAs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Power estimation techniques for FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Modeling routing demand for early-stage FPGA architecture development
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Wirelength modeling for homogeneous and heterogeneous FPGA architectural development
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Towards analytical methods for FPGA architecture investigation
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
An Analytical Model Relating FPGA Architecture to Logic Density and Depth
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Towards development of an analytical model relating FPGA architecture parameters to routability
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)
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We present an analytical model relating FPGA architectural parameters to the routability of the FPGA. The inputs to the model include the channel width and connection and switch block flexibilities, and the output is an estimate of the proportion of nets in a large circuit that can be expected to be routed on the FPGA. We assume that the circuit is routed to the FPGA using a single-step combined global/detailed router. Together with the earlier works on analytical modeling, our model can be used to predict the routability without going through an expensive CAD flow. We show that the model correctly predicts routability trends.