An Analytical Model Relating FPGA Architecture to Logic Density and Depth

Authors:
Joydip Das;Andrew Lam;Steven J. E. Wilton;Philip H. W. Leong;Wayne Luk
Affiliations:
Department of Electrical and Computer Engineering, University of British Columbia,;Department of Electrical and Computer Engineering, University of British Columbia,;Department of Electrical and Computer Engineering, University of British Columbia,;School of Electrical and Information Engineering, The University of Sydney,;Department of Computing, Imperial College London,
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2011

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Abstract

This paper presents an analytical model that relates FPGA architectural parameters to the logic size and depth of an FPGA implementation. In particular, the model relates the lookup-table size, the cluster size, and the number of inputs per cluster to the amount of logic that can be packed into each lookup-table and cluster, the number of used inputs per cluster, and the depth of the circuit after technology mapping and clustering. Comparison to experimental results shows that our model has good accuracy. We illustrate how the model can be used in FPGA architectural investigations to complement the experimental approach. The model's accuracy, combined with the simple form of the equations, make them a powerful tool for FPGA architects to better understand and guide the development of future FPGA architectures.