An analytical model relating FPGA architecture parameters to routability
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
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In the past 20 years, the capacity of FPGAs has grown by 200x and the speed has increased by 40x. Much of this dramatic improvement has been the result of architectural improvements. FPGA architectural enhancements are often developed in a somewhat ad-hoc manner. Expert FPGA architects perform experiments in which benchmark circuits are mapped using representative computer-aided design (CAD) tools, and the resulting density, speed, and/or power are estimated. Based on the results of these experiments, architects use their intuition and experience to design new architectures, and then evaluate these architectures using another set of experiments. This is repeated numerous times, until a suitable architecture is found. During this process, there is virtually no body of theory that architects can use to speed up their investigations. Such insight, however, would be extremely valuable. A better understanding of the tradeoff between flexibility and efficiency may allow FPGA architects to uncover improved architectures quickly. Although it is unlikely that such an understanding would immediately lead to an optimum architecture, it may provide the means to ”bound” the search space so that a wider variety of ”interesting” architectures can be experimentally evaluated. In this talk, I will describe recent work towards the development of such a theory. The current approach is to supplement the experimental methodology with a set of analytical expressions that relate architectural parameters to the area, speed, and power dissipation of an FPGA. Optimizing these analytical expressions is done using techniques such as geometric programming. I will summarize current research in this area, as well as try to provide some insight into how far we can go with these techniques.