Automatic design of reconfigurable domain-specific flexible cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wirelength modeling for homogeneous and heterogeneous FPGA architectural development
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
| Hi-index | 0.03 |
Interconnect prediction is very important for early feasibility studies in modern design flows. Most of the current interconnect estimation techniques estimate either the average or the total wirelength and some qualitative measure of routing demand for circuits. A priori techniques estimate these parameters without actually performing circuit placement. We propose a new a priori interconnect and wirelength estimation methodology for island style field programmable gate arrays (FPGAs). For a given design, we estimate bounding box semiperimeter wirelengths of all nets for an optimized placement and the minimum number of tracks per channel required for successful routing on an FPGA device. We analyze the structural characteristics of circuits and limitations posed by the FPGA architecture to derive a consistent model for wirelength and routing demand estimation. We identify reconvergences present in a circuit as an important global circuit characteristic in wirelength prediction. Our overall results show that we have an average error of 11.6% w.r.t. semiperimeter wirelength measured from the optimized layout using VPR. Also, the number of routing tracks per channel is predicted with an average error of 13.2% of the detailed routing results from VPR.