A coarse-grained FPGA architecture for high-performance FIR filtering

Authors:
James R. Anderson;Siddharth Sheth;Kaushik Roy
Affiliations:
Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA;Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA;School of Electrical Engineering, Purdue University, West Lafayette, IN
Venue:
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Year:
1998

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Abstract

This paper introduces a coarse-grained FPGA architecture that is specialized for high-performance Finite Impulse Response (FIR) filtering. The proposed architecture provides the flexibility of a DSP processor with performance and area efficiency similar to that of a custom ASIC design, while allowing all of the basic FIR design parameters, including coefficient precision, to be configured. Previous research has already shown that FPGAs can provide a high-performance alternative to DSP processors. Experimental comparisons in this paper show that the performance and area efficiency of the proposed architecture is similar to that of custom approaches across a wide range of filter sizes and configurations.