The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
On the Characterization of Multi-Point Nets in Electronic Designs
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Assessment of on-chip wire-length distribution models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry
Proceedings of the 2005 international workshop on System level interconnect prediction
IBM Journal of Research and Development - POWER5 and packaging
Impact of interconnect length changes on effective materials properties (dielectric constant)
Proceedings of the 2007 international workshop on System level interconnect prediction
Modeling routing demand for early-stage FPGA architecture development
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
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Rent's rule has been successfully applied to a priori estimation of wire length distributions. However, this approach is very restrictive: the circuits are assumed to be homogeneous. In this paper, recursive clustering is described as a more advanced model for the partitioning behavior of digital circuits. It is applied to predict the variance of the terminal count distribution. First, the impact of the block degree distribution is analyzed with a simple model. A more refined model incorporates the effect of stochastic self similarity. Finally, the model is further extended to describe the effects of heterogeneity. This model is a promising candidate for more accurate a priori estimation tools.