The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Efficient representation of interconnection length distributions using generating polynomials
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
On partitioning vs. placement rent properties
Proceedings of the 2001 international workshop on System-level interconnect prediction
On rent's rule for rectangular regions
Proceedings of the 2001 international workshop on System-level interconnect prediction
A differential equation for placement analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
A stochastic model for the interconnection topology of digital circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Generating synthetic benchmark circuits for evaluating CAD tools
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast estimation of the partitioning rent characteristic using a recursive partitioning model
Proceedings of the 2003 international workshop on System-level interconnect prediction
Assessment of on-chip wire-length distribution models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry
Proceedings of the 2005 international workshop on System level interconnect prediction
IBM Journal of Research and Development - POWER5 and packaging
Adaptable wire-length distribution with tunable occupation probability
Proceedings of the 2007 international workshop on System level interconnect prediction
Impact of interconnect length changes on effective materials properties (dielectric constant)
Proceedings of the 2007 international workshop on System level interconnect prediction
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Rent's rule based FPGA packing for routability optimization
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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Over the years, different interpretations of Rent's rule and different ways of estimating the Rent parameters have emerged. In general, these parameters are extracted from the average terminal-gate relationship for a set of circuit modules. We show that this relationship (the Rent characteristic) strongly depends on the definition of the circuit modules. These can be generated in many different ways, either from the topology of the circuit graph or, in a geometric way, by cutting regions from a circuit layout. The resulting Rent parameters can be quite far apart. This paper discusses the fundamental differences between the topological and the two geometric interpretations of the Rent characteristic that are expcted to be most appropriate for current wire-length estimation techniques. Our discussion is based on experimental data, as well as on a theoretical model that can be used to estimate certain geometric Rent charactristics from the topological Rent parameters. Using this model, we derive a theoretical lower limit to the value of the average geometric Rent exponent. we also study the impact of the placement approach and placement quality on the geometric Rent characteristics.