On the Characterization of Multi-Point Nets in Electronic Designs

  • Authors:
  • Dirk Stroobandt;Fadi J. Kurdahi

  • Affiliations:
  • -;-

  • Venue:
  • GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
  • Year:
  • 1998

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Abstract

Important layout properties of electronic designs include interconnection length values, clock speed, area requirements, and power dissipation. A reliable estimation of those properties is essential for improving placement and routing techniques for digital circuits.Previous work on estimating design properties failed to take multi-point nets into account. All nets were assumed to be 2-point nets (especially for estimating the number of nets). In this paper, we aim at characterizing multi-point nets in electronic designs. We will develop a model for the behaviour of multi-point nets during the partitioning process. The resulting distribution of nets over their net degree will be validated through comparison with benchmark data.