Interconnect implications of growth-based structural models for VLSI circuits

Authors:
Chung-Kuan Cheng;Andrew B. Kahng;Bao Liu
Affiliations:
UCSD Computer Science and Engineering Dept., La Jolla, CA;UCSD Computer Science and Engineering Dept., La Jolla, CA and UCSD Electrical and Computer Engineering Dept., La Jolla, CA;UCSD Computer Science and Engineering Dept., La Jolla, CA
Venue:
Proceedings of the 2001 international workshop on System-level interconnect prediction
Year:
2001

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Abstract

Power-law scaling phenomena that govern VLSI circuits have for several decades formed the foundation of VLSI interconnect estimation. This research investigates possible alternative power-law phenomena in VLSI circuits. In particular, we develop newrandom growthmodels and assess their implications for VLSI interconnect structure. We assess our models' predictions forfanout,crossing edge, andterminalscaling using test data from 21 industry standard-cell designs with up to 283K cells. Our work demonstrates the possibility of non-Rent based, yet equally plausible and well-fitting, structural models for VLSI circuits and their interconnections.