Efficient representation of interconnection length distributions using generating polynomials
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Prediction of interconnect fan-out distribution using Rent's rule
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Wiring layer assignments with consistent stage delays
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
On the Characterization of Multi-Point Nets in Electronic Designs
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
Toward accurate models of achievable routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Prediction of interconnect net-degree distribution based on Rent's rule
Proceedings of the 2004 international workshop on System level interconnect prediction
Assessment of on-chip wire-length distribution models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry
Proceedings of the 2005 international workshop on System level interconnect prediction
IBM Journal of Research and Development - POWER5 and packaging
Adaptable wire-length distribution with tunable occupation probability
Proceedings of the 2007 international workshop on System level interconnect prediction
A novel net-degree distribution model and its application to floorplanning benchmark generation
Integration, the VLSI Journal
A benchmark diagnostic model generation system
IEEE Transactions on Systems, Man, and Cybernetics, Part A: Systems and Humans - Special issue on model-based diagnostics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Interconnections are quickly becoming a dominant factor in the design of computer chips. Techniques to estimate interconnection lengths a priori (very early in the design flow) therefore gain attention and will become important for making the right design decisions when one still has the freedom to do so. However, at that time, one also knows least about the possible results of subsequent design steps. Conventional models for a priori estimation of wire lengths in computer chips use Rent's rule to estimate the number of terminals needed for communication between sets of gates. The number of interconnections then follows by taking into account that most nets are point-to-point connections. In this paper, we apply our previously introduced model for multiterminal nets to show that such nets have a fundamentally different influence on the wire length estimations than point-to-point nets. We then estimate the wire length distribution of Steiner tree lengths for applications related to routing resource estimation. Experiments show that the new estimated Steiner-length distributions capture the multiterminal effects much better than the previous point-to-point length distributions. The accuracy of the estimated values is still too low, as for the conventional point-to-point models, because we are still lacking a good model for placement optimization. However, the new results are a step closer to the application of wire length estimation techniques in real-world situations.