McPOWER: a Monte Carlo approach to power estimation
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Statistical estimation of the switching activity in digital circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
RASP: a general logic synthesis system for SRAM-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Efficient estimation of dynamic power consumption under a real delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Prediction of interconnect fan-out distribution using Rent's rule
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation
Proceedings of the 2003 international workshop on System-level interconnect prediction
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A Flexible Power Model for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs
Proceedings of the IEEE International Test Conference
Incremental placement for layout driven optimizations on FPGAs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
On the Interaction Between Power-Aware FPGA CAD Algorithms
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computers
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
Modeling routing demand for early-stage FPGA architecture development
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
The VTR project: architecture and CAD for FPGAs from verilog to routing
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Optimality Study of Logic Synthesis for LUT-Based FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Measuring the Gap Between FPGAs and ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Transition density: a new measure of activity in digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As capacity of the field-programmable gate arrays (FPGAs) continues to increase, power dissipated in the logic and routing resources has become a critical concern for FPGA architects. Recent studies have shown that static power is fast approaching the dynamic power in submicron devices. In this article, we propose an analytical model for relating homogeneous island-style-based FPGA architecture to static power. Current FPGA power models are tightly coupled with CAD tools. Our CAD-independent model captures the static power for a given FPGA architecture based on estimates of routing and logic resource utilizations from a pre-technology mapped netlist. We observe an average correlation ratio (C-Ratio) of 95% and a minimum absolute percentage error (MAPE) rate of 15% with respect to the experimental results generated by the Versatile Placement Routing (VPR) tool over the MCNC benchmarks. Our model offers application engineers and FPGA architects the capability to evaluate the impact of their design choices on static power without having to go through CAD-intensive investigations.