SRAM Leakage Suppression by Minimizing Standby Supply Voltage
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Two fast methods for estimating the minimum standby supply voltage for large SRAMs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a methodology for the optimal design of CMOS 6T SRAM ultra-low-power (ULP) bitcells minimizing power consumption under strict stability constraints in all operating modes. An accurate analytical SRAM subthreshold model is developed for characterizing the cell behavior and optimizing its performance. The proposed design approach is demonstrated for an SRAM implemented in a 32nm CMOS UTBB-FDSOI technology. Stable operation in both read and write is obtained for the optimized cell at VDD=0.4V. Moreover, in the optimization process the standby and active power were reduced up to 10x and 3x, respectively.