Using SimPoint for accurate and efficient simulation
SIGMETRICS '03 Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
SRAM Leakage Suppression by Minimizing Standby Supply Voltage
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Microarchitectural techniques for power gating of execution units
Proceedings of the 2004 international symposium on Low power electronics and design
Power Gating with Multiple Sleep Modes
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
The M5 Simulator: Modeling Networked Systems
IEEE Micro
Enhanced leakage reduction techniques using intermediate strength power gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic power gating with quality guarantees
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Power Management of Datacenter Workloads Using Per-Core Power Gating
IEEE Computer Architecture Letters
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power-efficient System Design
A Robust and Reconfigurable Multi-mode Power Gating Architecture
VLSID '11 Proceedings of the 2011 24th International Conference on VLSI Design
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
A case for guarded power gating for multi-core processors
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
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In mobile systems, the problems of short battery life and increased temperature are exacerbated by wasted leakage power. Leakage power waste can be reduced by power-gating a core while it is stalled waiting for a resource. In this work, we propose and model memory access power gating (MAPG), a low-overhead technique to enable power gating of an active core when it stalls during a long memory access. We describe a programmable two-stage power gating switch design that can vary a core's wake-up delay while maintaining voltage noise limits and leakage power savings. We also model the processor power distribution network and the effect of memory access power gating on neighboring cores. Last, we apply our power gating technique to actual benchmarks, and examine energy savings and overheads from power gating stalled cores during long memory accesses. Our analyses show the potential for over 38% energy savings given "perfect" power gating on memory accesses; we achieve energy savings exceeding 20% for a practical, counter-based implementation.