MAPG: memory access power gating
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Crank it up or dial it down: coordinated multiprocessor frequency and folding control
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Reliability improvement of logic and clock paths in power-efficient designs
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011
Full-Swing Gate Diffusion Input logic-Case-study of low-power CLA adder design
Integration, the VLSI Journal
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This book addresses power optimization in modern electronic and computer systems. Several forces aligned in the past decade to drive contemporary computing in the direction of low power and energy-awareness: the mobile revolution took the world by storm; power budgets forced mainstream processor designers to abandon the quest for higher clock frequency; and large data centers with overwhelming power costs began to play vital roles in our daily lives. Power optimization was elevated to a first class design concern, forcing everyone from the process engineer, circuit designer, processor architect, software developer, system builder, and even data center maintainer to make conscious efforts to reduce power consumption using myriad techniques and tools. This book explores power optimization opportunities and their exploitation at various levels of abstraction. Fundamental power optimizations are covered at each level of abstraction, concluding in a case study illustrating the application of the major techniques to a graphics processor. This book covers a comprehensive range of disparate power optimizations and is designed to be accessible to students, researchers, and practitioners alike.