High-Speed Clock Network Design
High-Speed Clock Network Design
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
IMPACT OF NEGATIVE BIAS TEMPERATURE INSTABILITY ON PRODUCT PARAMETRIC DRIFT
ITC '04 Proceedings of the International Test Conference on International Test Conference
Impact of NBTI on SRAM Read Stability and Design for Reliability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
NBTI Degradation: A Problem or a Scare?
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
On the efficacy of input Vector Control to mitigate NBTI effects and leakage power
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Analysis and optimization of NBTI induced clock skew in gated clock trees
Proceedings of the Conference on Design, Automation and Test in Europe
Power-efficient System Design
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Performance degradation due to transistor aging is a significant impediment to high-performance IC design due to increasing concerns of reliability mechanisms such as negative-bias-temperature-instability (NBTI). The concern only grows with technology scaling as the effects of positive bias temperature instability (PBTI) is becoming prominent in future technologies and compounding with the effects of NBTI. Although aging of transistor is inevitable and the magnitude of degradation due to aging varies depending upon the context. Specifically, in power-efficient systems designs, the logic and clock paths are susceptible to static stress resulting in peak degradation due to BTI occurrence when clock is gated. In this article, we present the reliability impact of making systems power efficient and propose a design-for-reliability methodology that can be used in conjunction with low-power design techniques to alleviate the stress conditions caused by rendering circuits in idle state. The technique—BTI-Refresh, is shown to be applicable to both logic and clock paths alike and focuses on preventing prolonged static stress using periodic refreshes to achieve alternating stress. The mechanism is shown to integrate seamlessly into the design at gate-level without requiring any architectural or RT-level changes. Using ISCAS benchmarks and Kogge-Stone-Adder circuits, it is shown to reduce the aging effect in logic path delay due to static stress by up to 50% with negligible area and power overhead. BTI-Refresh is extended to clock-paths to prevent pulse-width degradation due to static aging and with minimal clock-skew.