Stepwise sleep depth control for run-time leakage power saving
Proceedings of the great lakes symposium on VLSI
Testing for SoCs with advanced static and dynamic power-management capabilities
Proceedings of the Conference on Design, Automation and Test in Europe
MAPG: memory access power gating
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Multi-threshold CMOS is a very effective technique for reducing standby leakage power during long periods of inactivity. Recently, a power-gating scheme was presented to support multiple power-off modes and reduce the leakage power during short periods of inactivity. However, this scheme suffers from high sensitivity to process variations, which impedes manufacturability and also limits its applicability to at most two intermediate power-off modes. We propose a new power-gating technique that is tolerant to process variations and scalable to more than two intermediate power-off modes. In addition, the proposed design requires minimum design effort and offers greater power reduction and smaller area cost than the previous method. Analysis and extensive simulation results demonstrate the effectiveness of the proposed design.