SRAM Leakage Suppression by Minimizing Standby Supply Voltage
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Distributed Data-Retention Power Gating Techniques for Column and Row Co-Controlled Embedded SRAM
MTDT '05 Proceedings of the 2005 IEEE International Workshop on Memory Technology, Design, and Testing
3D-Stacked Memory Architectures for Multi-core Processors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Hybrid cache architecture with disparate memory technologies
Proceedings of the 36th annual international symposium on Computer architecture
PCRAMsim: system-level performance, energy, and area modeling for phase-change ram
Proceedings of the 2009 International Conference on Computer-Aided Design
3D integration: Circuit design, test, and reliability challenges
IOLTS '10 Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium
First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Computer Architecture, Fifth Edition: A Quantitative Approach
Computer Architecture, Fifth Edition: A Quantitative Approach
Design investigation of nanoelectronic circuits using crossbar-based nanoarchitectures
Microelectronics Journal
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As one of the newly introduced resistive random access memory (ReRAM) devices, this paper has shown an in-depth study of conductive-bridging random access memory (CBRAM) for non-volatile memory (NVM) computing. Firstly, a CBRAM-crossbar based memory is evaluated with accurate physical-level model and circuit-level characterization. It is then deployed as NVM component with a 3D hybrid integration of SRAM/DRAM, where one layer of CBRAM-crossbar is designed for data-retention under power gating to reduce leakage power from SRAM/DRAM at other layers. Moreover, a block-level data-retention scheme is designed to only write back dirty data from SRAM/DRAM to CBRAM-crossbar. When compared to the hybrid memory using phase-change random access memory (PCRAM) as data-retention, our CBRAM-based hybrid memory achieves 16x faster migration time and 4x less migration power for hibernating transition. When compared to the FeRAM-based bit-wise data-retention, our approach also achieves 17x smaller area and 8x smaller power under the same data migration speed.