Distributed Data-Retention Power Gating Techniques for Column and Row Co-Controlled Embedded SRAM

Authors:
Chung-Hsien Hua;Tung-Shuan Cheng;Wei Hwang
Affiliations:
National Chiao-Tung University;National Chiao-Tung University;National Chiao-Tung University
Venue:
MTDT '05 Proceedings of the 2005 IEEE International Workshop on Memory Technology, Design, and Testing
Year:
2005

Citing 0
Cited 2

Register file write data gating techniques and break-even analysis model

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, multi-mode data-retention power gating (P.G.) techniques are presented for embedded memories. These data retention power gating techniques are applied to embedded SRAM with distributed column and row co-controlled capabilities .The SRAM array is divided into blocks. Each block has a dedicated data-retention power gating device. The data-retention power gating devices are controlled by signals from both row and column decoders. Only the selected block is powered-on. Multi-mode power gating structures proposed in this paper can provide 2X to 20X memory cell leakage reduction while maintaining good static noise margin. Simulation results show that for a 64-bit wordline, the active power reductions for 32-bit, 16-bit, and 8-bit blocks are 59%, 79%, and 94%, respectively. All the simulations and physical layout are implemented in TSMC CMOS technology.