Register file write data gating techniques and break-even analysis model

Authors:
Eric Donkoh;Teck Siong Ong;Yan Nee Too;Patrick Chiang
Affiliations:
Intel Corporation, Hillsboro, OR, USA;Intel Corporation, Penang, Malaysia;Intel Corporation, Penang, Malaysia;Oregon State University, Corvallis, OR, USA
Venue:
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Year:
2012

Citing 3
Cited 1

Scaling of stack effect and its application for leakage reduction

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Energy: efficient instruction dispatch buffer design for superscalar processors

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Distributed Data-Retention Power Gating Techniques for Column and Row Co-Controlled Embedded SRAM

MTDT '05 Proceedings of the 2005 IEEE International Workshop on Memory Technology, Design, and Testing

A low-leakage dynamic register file with unclocked wordline and sub-segmentation for improved bitline scalability

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Register Files account for 30% of 32nm Intel WSM Core dynamic power of which 25% is due to write data distribution. We analyze Register File data gating strategies used to reduce write bitline dynamic power by as much as 96%. We explore the tradeoff of various data gating topologies (Global, Midway, Local), logic implementations (NAND, NOR, Tri-State), and techniques (Stack-Forcing, State-Forcing) to reduce both dynamic and leakage power. We then present a simple and accurate data gating break-even analysis model. The model comprehends "Data" and "Enable" switching activity, signal probability, logic implementation overhead, demonstrating an average error range of ±5%.