A low-leakage dynamic register file with unclocked wordline and sub-segmentation for improved bitline scalability

Authors:
Eric Donkoh;Patrick Chiang
Affiliations:
Intel Corporation, Hillsboro, OR, USA;Oregon State University, Corvallis, OR, USA
Venue:
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Year:
2012

Citing 2
Cited 0

Scaling of stack effect and its application for leakage reduction

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Register file write data gating techniques and break-even analysis model

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

Quantified Score

Hi-index	0.00

Visualization

Abstract

A register file is presented that uses an unclocked wordline with dynamic bitline sub-segmentation and stack-forcing to reduce both active and standby leakage. The proposed technique improves scalability to a larger number of entries per local bitline segment. For an example 32nm-CMOS 4-write, 6-read port 32 bits x 168 entries register file, the proposed bitline segmentation technique improves local bitline delay by 33%, lowers standby leakage by 70%, and reduces the number of clocked wordlines by 83% when compared with a conventional design. Furthermore, wordline sharing is shown to reduce the number of wordlines by as much as 58%.