Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Reliability-Aware Heterogeneous 3D Chip Multiprocessor Design
Journal of Electronic Testing: Theory and Applications
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3D-Stacked ICs (3D-SIC) based on Through-Silicon Vias (TSVs) offer alleviation of the performance and interconnect density bottlenecks faced by traditional CMOS scaling. As a result there is a lot of industrial focus to make this technology available for the next generation of SoCs. However, for 3D integration to become a viable product approach, it requires that the additional processing steps necessary preserve the integrity of both front-end and back-end of devices and constituting materials. 3D processing steps such as TSV insertion and wafer thinning, have an impact on the functionality and performance of analog and digital circuits, which needs to be accounted for during the design phase. Moreover, testing 3D-SICs calls for more complex test flow trade-offs and enhanced design-for-test architectures for test access within the stack. Finally, the reliability consequences with respect to thermal and mechanical stress in dense stacks of thinned wafers need to be carefully assessed to guarantee a target product life time. In this presentation we discuss the abovementioned challenges and some of the emerging solutions.