Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
Optimal topology exploration for application-specific 3D architectures
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Developing mesochronous synchronizers to enable 3D NoCs
Proceedings of the conference on Design, automation and test in Europe
Reliability aware through silicon via planning for 3D stacked ICs
Proceedings of the Conference on Design, Automation and Test in Europe
3D integration: Circuit design, test, and reliability challenges
IOLTS '10 Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium
Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs
Proceedings of the 49th Annual Design Automation Conference
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Ability to stack separate chips in a single package enables three-dimensional integrated circuits (3D ICs). Heterogeneous 3D ICs provide even better opportunities to reduce the power and increase the performance per unit area. An important issue in designing a heterogeneous 3D IC is reliability. To achieve this, one needs to select the data mapping and processor layout carefully. This paper addresses this problem using an integer linear programming (ILP) approach. Specifically, on a heterogeneous 3D CMP, it explores how applications can be mapped onto 3D ICs to maximize reliability. Preliminary experiments indicate that the proposed technique generates promising results in both reliability and performance.