Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
SRAM Leakage Suppression by Minimizing Standby Supply Voltage
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Review and future prospects of low-voltage RAM circuits
IBM Journal of Research and Development
Convergence of proportional-fair sharing algorithms under general conditions
IEEE Transactions on Wireless Communications
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Reducing leakage current in memories is critical for low-power designs in deep submicron technology. A common architectural technique consists of lowering the supply voltage to operate SRAM cells in sub-threshold (Vth). This paper investigates stability aspects of sub-Vth SRAM cells, both analytically and by simulation in STMicroelectronics' 90nm CMOS technology. For the first time analytical expressions for the Static Noise Margin in sub-Vth as a function of circuit parameters, operating conditions and process variations are derived. The 3G receiver case study illustrates the leakage saving potential of stable sub-Vth SRAM designs resulting into energy savings of up to 65%.