100MHz IDDQ Sensor Design with 1(A Resolution for BIST Applications

Authors:
Yann Antonioli;Shigeki Nishikawa;Hiroshi Uemura;Kozo Kinoshita
Affiliations:
-;-;-;-
Venue:
IDDQ '98 Proceedings of the IEEE International Workshop on IDDQ Testing
Year:
1998

Citing 0
Cited 1

Software-level instruction-cache leakage reduction using value-dependence of SRAM leakage in nanometer technologies

Transactions on high-performance embedded architectures and compilers III

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Abstract

This paper presents a high-speed, high-resolution IDDQ (power supply quiescent current) sensor design for BIST (Built-in Self Test) applications. The voltage drop is amplified before comparison with a reference voltage to improve sensing resolution. For various CUTs (Circuits Under Test) including Iscas circuits, Spice simulations show speeds up to 100MHz. A resolution better than 1驴EA is achieved while the voltage drop is kept under 0.3V.