Integer and combinatorial optimization
Integer and combinatorial optimization
The priority-based coloring approach to register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Memory segmentation to exploit sleep mode operation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A transformation-based approach for storage optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimal register assignment to loops for embedded code generation
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Array mapping in behavioral synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Low-power mapping of behavioral arrays to multiple memories
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Power exploration for data dominated video applications
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Performance-Power Optimization of Memory Components for Complex Embedded Systems
HICSS '97 Proceedings of the 30th Hawaii International Conference on System Sciences: Advanced Technology Track - Volume 5
Activity-sensitive architectural power analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Global register allocation for minimizing energy consumption
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
System-level power optimization: techniques and tools
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Code generation for embedded processors
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Efficient global register allocation for minimizing energy consumption
ACM SIGPLAN Notices
Early evaluation techniques for low power binding
Proceedings of the 2002 international symposium on Low power electronics and design
Data memory design considering effective bitwidth for low-energy embedded systems
Proceedings of the 15th international symposium on System Synthesis
Time-Energy Design Space Exploration for Multi-Layer Memory Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A memory aware behavioral synthesis tool for real-time VLSI circuits
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A trace-based binary compilation framework for energy-aware computing
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
A Progressive Register Allocator for Irregular Architectures
Proceedings of the international symposium on Code generation and optimization
Compiler-directed high-level energy estimation and optimization
ACM Transactions on Embedded Computing Systems (TECS)
Power-aware RAM mapping for FPGA embedded memory blocks
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
A global progressive register allocator
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Trace-based leakage energy optimisations at link time
Journal of Systems Architecture: the EUROMICRO Journal
Energy consumption analysis for two embedded Java virtual machines
Journal of Systems Architecture: the EUROMICRO Journal
Platform-based resource binding using a distributed register-file microarchitecture
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Buffer and Register Allocation for Memory Space Optimization
Journal of VLSI Signal Processing Systems
REWIRED: REgister Write Inhibition by REsource Dedication
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Register allocation for write activity minimization on non-volatile main memory
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Transactions on high-performance embedded architectures and compilers III
Trace-Based data cache leakage reduction at link time
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
An energy consumption model for an embedded java virtual machine
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Register allocation for write activity minimization on non-volatile main memory for embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
A compile-time managed multi-level register file hierarchy
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors
ACM Transactions on Computer Systems (TOCS)
Thermal-aware datapath merging for coarse-grained reconfigurable processors
Proceedings of the Conference on Design, Automation and Test in Europe
HLS-dv: a high-level synthesis framework for dual-Vdd architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Embedded Computing Systems (TECS)
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This paper presents for the first time low energy simultaneousmemory and register allocation. A minimum cost network flowapproach is used to efficiently solve for minimum energy dissipationsolutions in polynomial time. Results show that estimatedenergy improvements of 1.4 to 2.5 times over previous researchare obtained. This research is important for industry since energydissipation is minimized without requiring an increase in cost.