Spill code minimization techniques for optimizing compliers
PLDI '89 Proceedings of the ACM SIGPLAN 1989 Conference on Programming language design and implementation
On the Minimization of Loads/Stores in Local Register Allocation
IEEE Transactions on Software Engineering
ACM Letters on Programming Languages and Systems (LOPLAS)
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
Improvements to graph coloring register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Optimal register assignment to loops for embedded code generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Spill code minimization via interference region spilling
Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation
Low energy memory and register allocation using network flow
DAC '97 Proceedings of the 34th annual Design Automation Conference
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Optimal and near-optimal global register allocations using 0–1 integer programming
Software—Practice & Experience
Precise register allocation for irregular architectures
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the ninth annual ACM-SIAM symposium on Discrete algorithms
Optimal spilling for CISC machines with few registers
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
Compiling with code-size constraints
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Register allocation for irregular architectures
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Live Range Splitting in a Graph Coloring Register Allocator
CC '98 Proceedings of the 7th International Conference on Compiler Construction
Evaluation of Algorithms for Local Register Allocation
CC '99 Proceedings of the 8th International Conference on Compiler Construction, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS'99
A faster optimal register allocator
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Complete register allocation problems
STOC '73 Proceedings of the fifth annual ACM symposium on Theory of computing
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
A global progressive register allocator
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Optimistic coalescing for heterogeneous register architectures
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Register coalescing techniques for heterogeneous register architecture with copy sifting
ACM Transactions on Embedded Computing Systems (TECS)
Instruction selection by graph transformation
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Register loading via linear programming
WADS'11 Proceedings of the 12th international conference on Algorithms and data structures
Nearly optimal register allocation with PBQP
JMLC'06 Proceedings of the 7th joint conference on Modular Programming Languages
Performance characterization of the 64-bit x86 architecture from compiler optimizations' perspective
CC'06 Proceedings of the 15th international conference on Compiler Construction
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Register allocation is one of the most important optimizations a compiler performs. Conventional graph-coloring based register allocators are fast and do well on regular, RISC-like, architectures, but perform poorly on irregular, CISC-like, architectures with few registers and non-orthogonal instruction sets. At the other extreme, optimal register allocators based on integer linear programming are capable of fully modeling and exploiting the peculiarities of irregular architectures but do not scale well. We introduce the idea of a progressive allocator. A progressive allocator finds an initial allocation of quality comparable to a conventional allocator, but as more time is allowed for computation the quality of the allocation approaches optimal. This paper presents a progressive register allocator which uses a multi-commodity network flow model to elegantly represent the intricacies of irregular architectures. We evaluate our allocator as a substitute for gcc's local register allocation pass.