Graph coloring register allocation for processors with multi-register operands
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
ACM Letters on Programming Languages and Systems (LOPLAS)
Improvements to graph coloring register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
ACM Transactions on Programming Languages and Systems (TOPLAS)
Optimal and near-optimal global register allocations using 0–1 integer programming
Software—Practice & Experience
Precise register allocation for irregular architectures
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Optimal spilling for CISC machines with few registers
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Optimistic Register Coalescing
PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Taming the IXP network processor
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
Extending STI for demanding hard-real-time systems
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
A generalized algorithm for graph-coloring register allocation
Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation
A Progressive Register Allocator for Irregular Architectures
Proceedings of the international symposium on Code generation and optimization
Supporting Demanding Hard-Real-Time Systems with STI
IEEE Transactions on Computers
Minimizing bank selection instructions for partitioned memory architecture
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Journal of Systems and Software
Optimistic coalescing for heterogeneous register architectures
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
An Efficient Code Generation Algorithm for Non-orthogonal DSP Architecture
Journal of VLSI Signal Processing Systems
Minimal placement of bank selection instructions for partitioned memory architectures
ACM Transactions on Embedded Computing Systems (TECS)
Register allocation by puzzle solving
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
Generalized instruction selection using SSA-graphs
Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems
Aliased register allocation for straight-line programs is NP-complete
Theoretical Computer Science
Register coalescing techniques for heterogeneous register architecture with copy sifting
ACM Transactions on Embedded Computing Systems (TECS)
Transactions on Computational Science V
Instruction selection by graph transformation
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
SSA-based register allocation with PBQP
CC'11/ETAPS'11 Proceedings of the 20th international conference on Compiler construction: part of the joint European conferences on theory and practice of software
Decoupled graph-coloring register allocation with hierarchical aliasing
Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems
Nearly optimal register allocation with PBQP
JMLC'06 Proceedings of the 7th joint conference on Modular Programming Languages
CC'10/ETAPS'10 Proceedings of the 19th joint European conference on Theory and Practice of Software, international conference on Compiler Construction
Aliased register allocation for straight-line programs is NP-complete
ICALP'07 Proceedings of the 34th international conference on Automata, Languages and Programming
Constraint-Based register allocation and instruction scheduling
CP'12 Proceedings of the 18th international conference on Principles and Practice of Constraint Programming
Optimal register allocation in polynomial time
CC'13 Proceedings of the 22nd international conference on Compiler Construction
Optimal and heuristic global code motion for minimal spilling
CC'13 Proceedings of the 22nd international conference on Compiler Construction
ACM Transactions on Embedded Computing Systems (TECS)
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For irregular architectures global register allocation is still a challenging problem that has not been successfully solved so far. The graph-coloring analogy of traditional approaches does not match the needs of register allocation for such architectures which feature non-orthogonal instruction sets and small register files. This work proposes a fundamentally new approach to global register allocation for irregular architectures. Our approach formulates global allocation as a partitioned boolean quadratic optimization problem (PBQP) that allows generic modeling of processors peculiarities. Because PBQP is NP-complete we present a heuristic that exhibits a nearly linear run-time complexity.We integrated our register allocator with the Infineon Carmel C Compiler which is based on the Open Compiler Environment from Atair Software. A DSP benchmark suite was used to compare the performance of our register allocator with a graph-coloring approach and with an optimal allocation. The experiments show that our new approach performs better than a traditional graph coloring approach for irregular architectures.