Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Code scheduling and register allocation in large basic blocks
ICS '88 Proceedings of the 2nd international conference on Supercomputing
Global instruction scheduling for superscalar machines
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Efficiently computing static single assignment form and the control dependence graph
ACM Transactions on Programming Languages and Systems (TOPLAS)
Register allocation with instruction scheduling
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
A schedular-sensitive global register allocator
Proceedings of the 1993 ACM/IEEE conference on Supercomputing
Dependence-conscious global register allocation
Proceedings of the international conference on Programming languages and system architectures
Global code motion/global value numbering
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Register allocation sensitive region scheduling
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Proceedings of the 28th annual international symposium on Microarchitecture
Optimal instruction scheduling using integer programming
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Register allocation for irregular architectures
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
IEEE Transactions on Computers
A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Register Saturation in Superscalar and VLIW Codes
CC '01 Proceedings of the 10th International Conference on Compiler Construction
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Tetris: a new register pressure control technique for VLIW processors
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Optimal versus Heuristic Global Code Scheduling
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Combined code motion and register allocation using the value state dependence graph
CC'03 Proceedings of the 12th international conference on Compiler construction
Tree traversal scheduling: a global instruction scheduling technique for VLIW/EPIC processors
LCPC'01 Proceedings of the 14th international conference on Languages and compilers for parallel computing
Studying optimal spilling in the light of SSA
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Nearly optimal register allocation with PBQP
JMLC'06 Proceedings of the 7th joint conference on Modular Programming Languages
Integrated Code Generation for Loops
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Architecture and Code Optimization (TACO)
| Hi-index | 0.00 |
The interaction of register allocation and instruction scheduling is a well-studied problem: Certain ways of arranging instructions within basic blocks reduce overlaps of live ranges, leading to the insertion of less costly spill code. However, there is little previous research on the extension of this problem to global code motion, i.e., the motion of instructions between blocks. We present an algorithm that models global code motion as an optimization problem with the goal of minimizing overlaps between live ranges in order to minimize spill code. Our approach analyzes the program to identify the live range overlaps for all possible placements of instructions in basic blocks and all orderings of instructions within blocks. Using this information, we formulate an optimization problem to determine code motions and partial local schedules that minimize the overall cost of live range overlaps. We evaluate solutions of this optimization problem using integer linear programming, where feasible, and a simple greedy heuristic. We conclude that global code motion with the sole goal of avoiding spills rarely leads to performance improvements because code is placed too conservatively. On the other hand, purely local optimal instruction scheduling for minimal spilling is effective at improving performance when compared to a heuristic scheduler for minimal register use.