ACM Letters on Programming Languages and Systems (LOPLAS)
Improvements to graph coloring register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Operations research: deterministic optimization models
Operations research: deterministic optimization models
Optimal and near-optimal global register allocations using 0–1 integer programming
Software—Practice & Experience
Precise register allocation for irregular architectures
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Preference-directed graph coloring
PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
Register allocation for irregular architectures
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
A generalized algorithm for graph-coloring register allocation
Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation
A Progressive Register Allocator for Irregular Architectures
Proceedings of the international symposium on Code generation and optimization
A global progressive register allocator
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Register allocation via coloring of chordal graphs
APLAS'05 Proceedings of the Third Asian conference on Programming Languages and Systems
Minimal placement of bank selection instructions for partitioned memory architectures
ACM Transactions on Embedded Computing Systems (TECS)
Register allocation by puzzle solving
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
Generalized instruction selection using SSA-graphs
Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems
Instruction selection by graph transformation
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
SSA-based register allocation with PBQP
CC'11/ETAPS'11 Proceedings of the 20th international conference on Compiler construction: part of the joint European conferences on theory and practice of software
Optimal register allocation in polynomial time
CC'13 Proceedings of the 22nd international conference on Compiler Construction
Optimal and heuristic global code motion for minimal spilling
CC'13 Proceedings of the 22nd international conference on Compiler Construction
| Hi-index | 0.00 |
In this work we present a new heuristic for PBQP which significantly improves the quality of its register allocations and extends the range of viable target architectures. We also introduce a new branch-and-bound technique for PBQP that is able to find optimal register allocations. We evaluate each of these methods, as well as a state of the art graph colouring method, using SPEC2000 and IA-32 as a testbed. Spill costs are used as a metric for comparison. We provide experimental evidence that our new heuristic allows PBQP to remain effective even for relatively regular architectures such as IA-32, generating results equal to those of a start-of-the-art graph colouring technique. Our method is shown to run 3–4 times slower than graph colouring, however it supports a wide range of irregularities. Using our branch-and-bound solver for PBQP we were able to solve 97.4% of the functions in SPEC2000 optimally. These results are used as a yardstick to show that both PBQP and graph colouring produce results which are very close to optimal.